1. Field of the Invention
The present invention is directed in general to the field of semiconductor devices. In one aspect, the present invention relates to the fabrication of metal gate electrodes used in semiconductor devices.
2. Description of the Related Art
As semiconductor devices are scaled, aspects of device design and fabrication that previously gave rise to only second-order effects in long-channel devices can no longer be ignored. For example, the scaling of channel length and gate oxide thickness in a conventional MOS transistor exacerbates problems of polysilicon gate depletion, high gate resistance, high gate tunneling leakage current and dopant (i.e., boron) penetration into the channel region of the device. As a result, CMOS technology is increasingly replacing silicon dioxide gate dielectrics and polysilicon gate conductors with high dielectric constant (high-k) dielectrics in combination with metal gate electrodes formed from a gate stack of polysilicon and one or more metal layers. With such technologies, the metal gate layers not only obviate gate-depletion and boron-penetration effects, but also provide a significantly lower sheet resistance.
While high-k dielectrics in conjunction with metal gate electrodes advantageously exhibit improved transistor performance, the use of new metal layer technologies can create new technical challenges. For example, when the threshold voltage for metal gate PMOS devices is adjusted by including a silicon germanium layer in the PMOS channel region, the existing dual gate oxide (DGO) fabrication processes may not be compatible if they use thermal oxidation or high temperature thermal oxidation process to form the thick gate oxide over the silicon germanium layer. This is because the high temperature process causes the germanium to diffuse into the regions of the substrate or the gate oxide that should not contain any germanium, thereby degrading the profile of the silicon germanium channel. Thermal oxidation of a silicon germanium channel layer can also create high interface state density that can adversely affect core and DGO device performance by creating a serious Time-Dependent Dielectric Breakdown (TDDB) issue.
Accordingly, a need exists for an improved metal gate electrode and manufacture method for an improved dual gate oxide device integration which incorporates one or more high-k gate dielectric materials to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.